. IEEE 1364 reference model & event queue. Triggers testbench stimulus commands @negedge clk. Two output taps Both models use Verilog-2001 enhanced. The PFEventTaps Framework was created in 2007 as the engine underlying PFiddlesoft's free Event Taps Testbench utility for developers. The framework supports and enhances Apple's Quartz Event Taps.

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What is testbench top module ?

All verification components, interfaces and DUT are instantiated in a top levelmodule called testbench. It is a static container to hold everything required to be simulated and becomes the root node in the hierarchy. This is usually named tb or tb_top although it can assume any other name.

Simulators typically need to know the top level module so that it can analyze components within the top module and elaborate the design hierarchy.

Click here to know more about top level modules !

Testbench Top Example

The example below details the elements inside the top module tb_top.

Note the following :

• tb_top is a module and is a static container to hold everything else
• It is required to import uvm_pkg in order to use UVM constructs in this module
• Clock is generated in the testbench and passed to the interface handle dut_if1
• The interface is set as an object in uvm_config_db via set and will be retrieved in the test class using get methods
• The test is invoked by run_test method which accepts name of the test class base_test as an argument
• Call waveform dump tasks if required

Clock generation

A real design may have digital blocks that operate on multiple clock frequencies and hence the testbench would need to generate multiple clocks and provide as an input to the design. Hence clock generation may not be as simple as an always block shown in the example above. In order to test different functionalities of the design, many clock parameters such as frequency, duty cycle and phase may need to be dynamically updated and the testbench would need infrastructure to support such dynamic operations.

The approach shown above may not be scalable and need to be driven from the testbench using hierarchical signal paths since they are instantiated as modules. A better UVM alternative is to create an agent for the clock so that it can be easily controlled from sequence and tests using agent configuration objects.

Reset Generation

In a similar way, a reset agent can be developed to handle all reset requests. In many systems, there are two kinds of reset - hardware and software. A software reset is typically done through a register model and would be separate from a reset agent. Hardware resets include assertion of the system reset pin for a given duration or follow a certain sequence of events before the actual reset is applied. All such scenarios can be handled separately using this reset agent which needs a handle to the reset interface.

Creation of internal tap points

Some testbench components may rely on tapping internal nets in the design to either force or sample values to test certain features. These internal nets may need to be assigned to a different value based on input stimuli and can be done so in the top level testbench module. Such signals can be tied to a generic interface and be driven from another agent.

Event Taps Testbench Reviews

Learn how run_test() starts the actual UVM test from this blog post.